1) Field of the Invention
The present invention relates to the technique for translating virtual addresses into physical addresses in an information processor, which operates in multi-thread mode.
2) Description of the Related Art
Conventionally, in an information processor comprising a processor (e.g., CPU: Central Processing Unit or MPU; Micro Processing Unit), there has been a technique wherein a TLB (Translation Lookaside Buffer; an address translation buffer) is provided in the processor (here, CPU) for translating virtual addresses used by the program into physical addresses on a storage (e.g., main memory or cache memory connected to the information processor) which stores the data in the information processor.
The TLB stores address translation pairs (TLB entry) indicating the correspondence between virtual addresses and physical addresses. Using the TLB, the CPU enables high-speed address translation from virtual addresses into physical addresses.
Although address translation pairs to be stored in the TLB are registered by the OS (Operating System) of the information processor, the OS may, on rare occasions, register a plurality of identical address translation pairs.
Thus, if a plurality of identical address translation pairs are registered in the TLB, Multi-Hits are detected by retrieving (referring to) these plurality of address translation pairs when actually executing address translation.
FIG. 8 is an illustration for explaining the multi-hit detection method in a conventional information processor 110. In a conventional information processor 110, the TLB 111 is retrieved and a TLB entry of a virtual address identical to the virtual address to be translated is retrieved in order to translate the virtual address. Then, in the case where, according to the result of retrieval, there is a matching entry (a hit is found) in terms of the TLB entry A (expressed as “entry A” in FIG. 8) stored in WAY 0 (here a WAY refers to a segment of TLB divided into a plurality of segments) of the TLB 111 and the TLB entry B (expressed as “entry B” in FIG. 8) of WAY 1, multi-hits are outputted by a multi-hit controller 112 provided in the information processor 110 if TLB entries A and B are identical.
If multi-hits are detected, the conventional information processor 110, regarding the data (address translation pairs) stored in the TLB 111 as unreliable, deletes and re-register all the address translation pairs stored in the TLB 111, thereby causing a penalty to occur, the penalty being delaying the operation in the CPU during the deletion and re-registration of all the address translation pairs stored in the TLB 111.
In this context, there has been proposed as a method of controlling multi-hits of the TLB, a technique wherein it is checked whether or not a TLB entry is already registered on the TLB when writing a new TLB entry (address translation pair) into the TLB, and, if there exists a TLB entry identical to the TLB entry to be newly written, there is performed overwriting of the already registered TLB entry with the TLB entry to be newly written (see patent document 1 in the following).
In addition, in a technique related to a cache memory device, there has been proposed a technique wherein in the case where a plurality of hits are found in terms of identical data on the cache memory cache-miss is established and the data thereon are deleted (see the following patent document 2).
[patent document 1] Japanese translation of published PCT international patent applications No. Hei 11-501745
[patent document 2] Japanese Patent Laid-Open (Kokai) Hei 2-300951
Now, in recent years, there have been widely used multi-threaded computing techniques, which enable a plurality of threads to run on the processor core of a single CPU. By employing the multi-thread mode, a process including translation of virtual addresses into physical addresses may be assigned to a plurality of different threads (here thread 0 and thread 1) with time intervals therebetween. In such a case, since thread 0 and thread 1 both use the identical address translation pair, it is desirable that TLB resources be shared by the plurality of threads 0 and 1. Thus, sharing TLB resources by a plurality of threads 0 and 1 can improve utilization efficiency of the TLB.
In the conventional technique, however, sharing TLB resources between a plurality of threads 0 and 1 results in undesirable multi-hits, such multi-hits causing said penalty to occur, thereby leading to performance degradation (delay of processing) of the CPU. Undesirable multi-hits are not attributed to malfunction of the OS but to occurrence of TLM misses such as nonexistence of the virtual address to be translated on the TLB. In short, undesirable multi-hits are caused by a plurality of threads 0 and 1 executing simultaneously a process called TLB miss handler, which, due to occurrence of a TLB miss, reads out a page table entry from the main memory, or the like, of the information processor so as to register it in TLB.
FIG. 9 is a flow chart (step S10 to S15) for explaining the cause of occurrence of undesirable multi-hits when the TLB is shared between plural threads in an information processor employing the conventional multi-thread mode. As shown in FIG. 9, in the case where the TLB is shared between a plurality of threads (here, threads 0 and 1) in the information processor employing the conventional multi-thread method, when thread 0 causes a TLB miss to occur during execution of thread 0 (step S10), thread 0 executes the TLB miss handler (TLB entry registration process) (step S11). Now, if thread 0 causes a cache-miss to occur during execution of the TLB miss handler (step S12), this cache miss triggers thread switching, which switches the process in the information processor from thread 0 to thread 1.
Then, if during execution of thread 1, a TLB miss is detected in thread 1 at a virtual address identical to the virtual address in which thread 0 caused the TLB miss (step S13), thread 1 executes the TLB miss handler (TLB entry registration process) (step S14).
After the TLB miss handler of thread 1 is finished (TLB entry registration completion), switching of threads is triggered again, and the process is switched from thread 1 to thread 0, which in turn resumes the TLB miss handler with regard to thread 0 which was sleeping until then (step S15), and thread 0 also completes the TLB miss handler.
Execution of such a process results in the existence of two identical TLB entries on the TLB by the TLB miss of threads 0 and 1. Thus, undesirable multi-hits are detected by referring to these identical TLB entries for subsequent address translation.